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M41T256Y
256Kbit (32K x 8) serial RTC
Not For New Design
Features

5V operating voltage Serial interface supports extended I2C bus addressing (400kHz) Automatic switchover and deselect circuitry Power-fail deselect voltages: - M41T256Y: VCC = 4.5 V to 5.5V; VPFD = 4.2V < VPFD < 4.5V Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year Programmable software clock calibration 32,752 bytes of general purpose RAM Microprocessor power-on reset Holds microprocessor in reset until supply voltage reaches stable operating level Automatic address-incrementing Tamper indication circuit with time-stamp Sleep mode function Available in ST's 44-lead SNAPHAT(R) SOIC mates with ST's removable/replaceable SNAPHAT(R) battery/crystal top (ordered separately) RoHS compliant - Lead-free second level interconnect
SOH44 (MH)
44 1
SNAPHAT (SH) crystal/battery

November 2007
Rev 5
1/30
www.st.com 1
This is information on a product still in production but not recommended for new designs.
Contents
M41T256Y
Contents
1 2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 2.3 2.4 2.5
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Tamper indication circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Preferred power-on/battery attach defaults . . . . . . . . . . . . . . . . . . . . . . . 21
4 5 6 7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M41T256Y
Contents
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
List of tables
M41T256Y
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TIMEKEEPER(R) register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SOH44 - 44-lead plastic small outline, SNAPHAT, package mech. data. . . . . . . . . . . . . . 26 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data. . . . . . . . . 27 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SNAPHAT(R) battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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M41T256Y
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 44-pin SOIC (MH - snaphat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SOH44 - 44-lead plastic small outline, SNAPHAT, package outline . . . . . . . . . . . . . . . . . 26 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal outline . . . . . . . . . . . . . . . . . 27
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Summary
M41T256Y
1
Summary
The M41T256Y Serial TIMEKEEPER(R) SRAM is a low power 256Kbit static CMOS SRAM organized as 32K words by 8 bits. A built-in 32.768kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 3 on page 18) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T256Y has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, and power-on reset. The eight clock address locations contain the year, month, date, day, hour, minute, second, and tenths/hundredths of seconds in 24hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The first clock address location (7FF8h) stores the clock software calibration settings as well as the write clock bit. The M41T256Y is supplied in a 44-lead SOIC SNAPHAT(R) package (MH - which integrates both crystal and battery in a single SNAPHAT top). The 44-pin, 330mil SOIC provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface-mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 44-pin SOIC and crystal/battery packages are shipped separately in plastic, anti-static tubes or in Tape & Reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4TxxBR12SH" (see Table 14 on page 28).
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium, button-cell battery.
6/30
M41T256Y Figure 1. Logic diagram
VCC
Summary
SCL RST SDA TP M41T256Y FT
VSS
AI04754b
1. For 44-pin SNAPHAT (MT) package only.
Table 1.
FT RST SCL SDA VCC VSS TP
Signal names
Frequency test (open drain) Reset output (open drain) Serial clock input Serial data input/output Supply voltage Ground Tamper input
7/30
Summary Figure 2. 44-pin SOIC (MH - snaphat)
NC NC NF RST NF NF NF NF NF NF NF TP NC NF NF NF NF SDA VSS VSS NC VSS 44 1 2 43 3 42 4 41 40 5 39 6 7 38 8 37 9 36 35 10 11 M41T256Y 34 12 33 13 32 14 31 15 30 29 16 17 28 27 18 26 19 20 25 21 24 22 23 VCC NC NC NC FT NF NF NF NF NF NF NC NC NF SCL NC NF NF NF NF NF NC
AI07022
M41T256Y
Figure 3.
Block diagram
PULL-UP TO CHIP VCC SDA I2C INTERFACE SCL REAL TIME CLOCK CALENDAR 32,752 BYTES USER RAM RTC & CALIBRATION TAMPER BIT FT(1)
Crystal
32KHz OSCILLATOR
TP VCC POWER
VBAT VBL= 2.5V COMPARE BL
VSO = VBAT VPFD = 4.38V
COMPARE
COMPARE
POR
RST(1)
AI04759
1. Open drain output
8/30
M41T256Y
Operating modes
2
Operating modes
The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 256K bytes contained in the device can then be accessed sequentially in the following order: 0-7FEF = General purpose RAM 7FF0-7FF6 = Reserved 7FF7h = Tenths/hundredths register 7FF8h = Control register 7FF9h = Seconds register 7FFAh = Minutes register 7FFBh = Hour register 7FFCh = Tamper/day register 7FFDh = Date register 7FFEh = Month register 7FFFh = Year register The M41T256Y clock continually monitors VCC for an out-of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD plus tREC. For more information on Battery Storage Life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
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Operating modes
M41T256Y
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge clock pulse. This acknowledge clock pulse is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
10/30
M41T256Y Figure 4. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
Operating modes
(SCL) CLOCK
(SDA) DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI04756
Figure 5.
Acknowledgement sequence
START CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
SCL FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
11/30
Operating modes Figure 6. Bus timing requirements sequence
M41T256Y
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Table 2.
Symbol fSCL tBUF tF tHD:DAT tHD:STA tHIGH tLOW tR tSU:DAT(2) tSU:STA tSU:STO
AC characteristics
Parameter(1) SCL clock frequency Time the bus must be free before a new transmission can start SDA and SCL fall time Data hold time START condition hold time (after this period the first clock pulse is generated) Clock high period Clock low period SDA and SCL rise time Data setup time START condition setup time (only relevant for a repeated start condition) STOP condition setup time 100 600 600 0 600 600 1.3 300 Min 0 1.3 300 Max 400 Unit kHz s ns s ns ns s ns ns ns ns
1. Valid for ambient operating temperature: TA = -25 to 70C; VCC = 4.5 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL
2.2
Read mode
In this mode the master reads the M41T256Y slave after setting the slave address (see Figure 7 on page 13). Following the WRITE mode control bit (R/W=0) and the Acknowledge Bit, the byte addresses A(0) and A(1) are written to the on-chip address pointer (MSB of address byte A(0) is a "Don't care"). Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the
12/30
M41T256Y
Operating modes master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 8 on page 14).
Note:
Address pointer will wrap around from maximum address to minimum address if consecutive READ or WRITE cycles are performed. An alternate READ mode may also be implemented whereby the master reads the M41T256Y slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9 on page 14).
Figure 7.
Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Note:
The most significant bit is sent first.
13/30
Operating modes Figure 8. Read mode sequence
M41T256Y
START
START
BUS ACTIVITY: MASTER SDA LINE
R/W
S
ACK
BYTE ADDRESS (0)
ACK
BYTE ADDRESS (1)
ACK
S
ACK
R/W
DATA n
ACK
AI04760
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
NO ACK
Figure 9.
Alternate read mode sequence
START START
BUS ACTIVITY: MASTER SDA LINE
R/W
S
ACK
BYTE ADDRESS (0)
ACK
BYTE ADDRESS (1)
ACK
S
ACK
R/W
DATA n
ACK
AI04760
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
NO ACK
14/30
M41T256Y
Operating modes
2.3
Write mode
In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol is shown in Figure 10 on page 15. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that byte addresses A(0) and A(1) will follow and is to be written to the on-chip address pointer (MSB of address byte A(0) is a "Don't care"). The data byte to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge bit. The M41T256Y slave receiver will send an acknowledge bit to the master transmitter after it has received the slave address (see Figure 7 on page 13) and again after it has received each address byte.
Figure 10. Write mode sequence
START R/W STOP
BUS ACTIVITY: MASTER SDA LINE
S
ACK
BYTE ADDRESS (0)
ACK
BYTE ADDRESS (1)
ACK
DATA n
ACK
DATA n+X
P
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI04761
2.4
Data retention mode
With valid VCC applied, the M41T256Y can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M41T256Y will automatically deselect, write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is accomplished by internally inhibiting access to the clock registers. At this time, the reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls below the battery back-up switchover voltage (VSO), power input is switched from the VCC pin to the external battery and the clock registers and SRAM are maintained from the attached battery supply. All outputs become high impedance. On power up, when VCC returns to a nominal value, write protection continues for tREC. The RST signal also remains active during this time (see Figure 14 on page 25). For a further more detailed review of lifetime calculations, please see Application Note AN1012.
15/30
Operating modes
M41T256Y
2.5
Sleep mode
In order to minimize the battery current draw while in storage, the M41T256Y provides the user with a battery "sleep mode," which disconnects the RAM memory array from the external Lithium battery normally used to provide non-volatile operation in the absence of VCC. This can significantly extend the lifetime of the battery, when non-volatile operation is not needed.
Note:
The sleep mode will remove power from the RAM array only and not affect the data retention of the TIMEKEEPER Registers (7FF0h through 7FFFh - this includes the Calibration Register). The sleep mode (SLP) Bit located in register 7FF8h (D6), must be set to a '1' by the user while the device is powered by VCC. This will "arm" the sleep mode latch, but not actually disconnect the RAM array from power until the next power-down cycle. This protects the user from immediate data loss in the event he inadvertently sets the SLP Bit. Once VCC falls below VSO (VBAT), the sleep mode circuit will be engaged and the RAM array will be isolated from the battery, resulting in both a lower battery current, and a loss of RAM data.
Note:
Upon initial battery attach or initial power application without the battery, the state of the SLP Bit will be undetermined. Therefore, the SLP Bit should be initialized to '0' by the user. Additional current reduction can be achieved by setting the STOP (ST) Bit in register 7FF9h (D7), turning off the clock oscillator. This combination will result in the longest possible battery life, but also loss of time and data. When the device is again powered-up, the user should first read the SLP Bit to determine if the device is currently in sleep mode, then reset the bit to '0' in order to disable the sleep mode (this will NOT be automatically taken care of during the power-up).
Note:
See AN1570, "M41T256Y Sleep Mode Function" for more information on sleep mode and battery lifetimes.
16/30
M41T256Y
Clock operation
3
Clock operation
Year, month, and date are contained in the last three registers of the TIMEKEEPER(R) register map (see Table 3 on page 18). Bits D0 through D2 of the next register contain the day (day of week). Finally, there are the registers containing the seconds, minutes, and hours, respectively. The first clock register is the control register (this is described in the clock calibration section). The nine clock registers may be read one byte at a time, or in a sequential block. The control register (Address location 7FF8h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the nine clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the read.
3.1
Reading the clock
The nine byte clock register (see Table 3 on page 18) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (7FF9h to 7FFFh). The update will resume either due to a stop condition or when the pointer increments to a RAM address. This prevents reading data in transition. The TIMEKEEPER(R) cells in the register map are only data registers and not actual clock counters, so updating the registers can be halted without disturbing the clock itself.
3.2
Setting the clock
Bit D7 of the control register (7FF8h) is the write clock bit. Setting the write clock bit to a '1' will allow the user to write the desired day, date, and time data in 24-hour BCD format. Resetting the write clock bit to a '0' then transfers the values of all time registers (7FF8h7FFFh) to the actual clock counters and resets the internal divider (or clock) chain.
Note:
The tenths/hundredths of seconds register will automatically be reset to zero when the WRITE clock bit is set. Other register bits such as FT, TEB, and ST may be written without setting the WC Bit. In such cases, the clock data will be undisturbed and will retain their previous values.
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The stop bit (ST) is the most significant bit of the seconds register. Setting it to '1' stops the oscillator. Setting it to '0' restarts the oscillator in approximately one second.
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Clock operation Table 3.
Address D7 7FFFh 7FFEh 7FFDh 7FFCh 7FFBh 7FFAh 7FF9h 7FF8h 7FF7h 7FF6h 7FF5h 7FF4h 7FF3h 7FF2h 7FF1h 7FF0h X X X X X X X 0 0 BL 0 0 ST WC D6 D5 D4 D3 D2 Year 10M Month Date: Day of Month 0 Day of Week D1 D0 10 years 0 0 FT 0 0
M41T256Y TIMEKEEPER(R) register map
Data Function/Range BCD Format Year Month Date Tamper/day Hours Minutes Seconds Control Seconds X X X X X X X Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00-99 00-99 01-12 01-31 0-1/01-07 00-23 00-59 00-59
10 date TEB TB
10 hours 10 minutes 10 seconds
Hours (24 Hour Format) Minutes Seconds Calibration 0.01 Seconds
SLP
S
0.1 Seconds X X X X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X
X X X X X X X
Keys: S = Sign bit FT = Frequency test bit ST = Stop bit WC = Write clock bit X = '1' or '0' BL = Battery low flag (read only bit) TB = Tamper bit (read only bit) TEB = Tamper enable bit 0 = Must be set to '0' SLP = Sleep mode bit Note: 7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.
3.4
Power-on reset
The M41T256Y continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time.
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M41T256Y
Clock operation
3.5
Tamper indication circuit
The M41T256Y provides an independent input pin, the tamper pin (TP) which can be used to monitor a signal which can result in the setting of the tamper bit (TB) if the tamper enable bit (TEB) is set to a '1.' The tamper pin is triggered by being connected to VCC/VBAT through an external switch. This switch is normally open in the application, allowing the pin to be "floating" (internally latched to VSS when TEB is set). When this switch is closed (connecting the pin to VCC/VBAT), the tamper bit will be immediately set. This allows the user to determine if the device has been physically moved or tampered with. The tamper bit is a "read only" bit and is reset only by taking the tamper pin to ground and resetting the tamper enable bit to '0.' This function operates both under normal power, and in battery back-up. If the switch closes during a power-down condition, the bit will still be set correctly.
Note:
Upon initial battery attach or initial power application without the battery, the state of TEB (and TB) will be undetermined. Therefore TEB must be initialized to a '0.'
3.6
Tamper event time-stamp
If a tamper occurs, not only will the tamper bit be set, but the event will also automatically be time-stamped. This is accomplished by freezing the normal update of the clock registers (7FF7h through 7FFFh) immediately following a tamper event. Thus, when tampering occurs, the user may first read the time registers to determine exactly when the tamper event occurred, then re-enable the clock update to the current time (and reset the Tamper Bit, TB) by resetting the tamper enable bit (TEB). The time update will then resume, and after either a stop condition or incrementing the address pointer to a RAM address and back, the clock can be read to determine the current time.
Note:
The tamper bit (TB) must always be set to '0' in order to read the current time.
3.7
Calibrating the clock
The M41T256Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not exceed 35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about 1.53 minutes per month. When the calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 11 on page 20). Therefore, the M41T256Y design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 20. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register (7FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
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Clock operation
M41T256Y
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Figure 11. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T -T )2 O F K = -0.036 ppm/C2 0.006 ppm/C2 TO = 25C 5C
Temperature C
AI00999b
Figure 12. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
Two methods are available for ascertaining how much calibration a given M41T256Y may require.
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M41T256Y
Clock operation The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the FT pin. The pin will toggle at 512Hz, when the stop bit (ST) is '0,' and the frequency test bit (FT) is '1.' Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. The FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
3.8
Battery low warning
The M41T256Y automatically performs battery voltage monitoring upon power-up. The battery low (BL) bit, bit D7 of day register, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, during the next power-up sequence. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. The battery may be replaced while VCC is applied to the device. The M41T256Y only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
3.9
Preferred power-on/battery attach defaults
See Table 4, below. Table 4. Preferred default values
Condition Battery attach or initial power-up Power-cycling (with battery)
1. X = Undetermined; UC = Unchanged
WC 0 0
TEB(1) X UC
TB(1) X UC
FT 0 0
ST(1) X UC
SLP(1) X UC
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Maximum rating
M41T256Y
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5.
Symbol TSTG TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation SNAPHAT(R) SOIC Value -40 to 85 -55 to 125 260 -0.3 to VCC + 0.3 -0.3 to 7.0 20 1 Unit C C C V V mA W
1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M41T256Y
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 6: DC and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. DC and AC measurement conditions
Parameter VCC Supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M41T256Y 4.5 to 5.5V -25 to 70C 100pF 50ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Figure 13. AC testing input/output waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 7.
Symbol CIN CIO(3) tLP
Capacitance
Parameter(1) and (2) Input capacitance Input capacitance (tamper pin) Input / output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 1000 10 50 Unit pF pF pF ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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DC and AC parameters Table 8.
Sym IBAT ICC1 ICC2 ILI ILO(2) VIH VIHB VIL VOH VOL
M41T256Y
DC characteristics
Parameter Test condition(1) TA = 25C, VCC = 0V, VBAT = 3.0V f = 400kHz SCL, SDA = VCC - 0.3V 0V VIN VCC 0V VOUT VCC 0.7VCC VBAT - Vdiode -0.3 2.5 Min Typ 1.5 1.0 1.4 1.0 Max 1.9 1.4 3.0 2.5 1 1 VCC + 0.3 VBAT 0.3VCC 3.5 VCC + 0.3 IOL = 3.0mA IOL = 10mA 4.20 VBAT 500 0.4 0.4 4.50 Unit A A mA mA A A V V V V V V V V V W
Battery current OSC ON Battery current OSC OFF Supply current Supply current (standby) Input leakage current Output leakage current Input high voltage Input high voltage in battery back-up for tamper pin Input low voltage
VBAT Battery voltage Output high voltage Output low voltage Output low voltage (open drain)(3)
VPFD Power fail deselect VSO RSW Battery back-up switchover Switch resistance on tamper pin
1. Valid for ambient operating temperature: TA = -25 to 70C; VCC = 4.5 to 5.5V (except where noted). 2. Outputs deselected. 3. For RST and FT pin (open drain).
Table 9.
Symbol f0 RS CL
Crystal electrical characteristics (externally supplied)
Parameter(1) Resonant frequency Series resistance Load capacitance 12.5 Typ 32.768 35 Min Max Unit kHz k pF
1. Load capacitors are integrated within the M41T256Y. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
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M41T256Y Figure 14. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tDR tRB
DC and AC parameters
tR tREC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI04757
Table 10.
Symbol tF(2) tFB(3) tR tRB tREC tDR
Power down/up AC characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time Power up deselect time Expected data retention time (OSC on, sleep mode off) Min 300 10 10 1 40 7.2(4) 200 Typ Max Unit s s s s ms years
1. Valid for ambient operating temperature: TA = -25 to 70C; VCC = 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. At 25C and VCC = 0V with the oscillator running and using M4T32-BR12SH SNAPHAT battery top.
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Package mechanical data
M41T256Y
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 15. SOH44 - 44-lead plastic small outline, SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 11.
Symb Typ A A1 A2 B C D E e eB H L a N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 44 0.10 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.142 0.500 0.050 8
SOH44 - 44-lead plastic small outline, SNAPHAT, package mech. data
mm inches
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M41T256Y
Package mechanical data Figure 16. SH - 4-pin SNAPHAT housing for 120mAh battery & crystal outline
A2 A A3
A1
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 12.
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090
SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data
mm inches
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Part numbering
M41T256Y
7
Table 13.
Example: Device type M41T
Part numbering
Ordering information scheme
M41T 256Y MT 7 E
Supply voltage and write protect voltage 256Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Package MH(1) = SOH44 Temperature range 7 = -25 to 70C Shipping method E = Lead-free package (ECOPACK(R)), tubes F = Lead-free package (ECOPACK(R)), tape & reel
1. The SOIC package (SOH44) requires the SNAPHAT(R) battery package which is ordered separately under the part number "M4Txx-BR12SH" in plastic tubes (see Table 14).
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
Table 14.
SNAPHAT(R) battery table
Description Lithium battery (120mAh) SNAPHAT Package SH
Part Number M4T32-BR12SH
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M41T256Y
Revision history
8
Revision history
Table 15.
Date February 2002 26-Apr-02 31-May-02 03-Jul-02 12-Jul-02 29-Jul-02 20-Dec-02 04-Jan-03 26-Mar-03 15-Jun-04
Document revision history
Version 1.0 1.1 1.2 1.3 1.4 1.5 2.0 2.1 2.2 3.0 First Issue Addition of "Tamper Event Time-Stamp" text Add Sleep Mode, 44-pin with SNAPHAT package (Figure 2, 5, 19, 20; Table 1, 5, 14, 15, 12, 13). Modify Crystal Electrical Characteristics table footnotes (Table 9). Added programmable Sleep Mode information to document (Figure 3, 4, 5, 6; Table 3, 4) Add "Hatless" to package description (Figure 1,18) and Table 14, 11) ICC Characteristics changed (Table 8); Document promoted to "Datasheet" Add VOL value (Table 8) Update test condition (Table 10) Reformatted; add Lead-free information; update characteristics (Figure 14; Table 5, 14) Reformatted document. Updated packaging references that only 44-lead SNAPHAT available (cover page, Summary, Figure 1, Table 1, Table 13). Updated Table 9, 10. Added lead-free second level interconnect information to cover page and Section 6: Package mechanical data; product status "Not for New Design"; updated Table 13. Revision Details
16-Apr-2007
4
09-Nov-2007
5
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M41T256Y
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